(1) Field of the Invention
This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which excels in high speed operation.
(2) Description of the Related Art
For a method for manufacturing a semiconductor device, a technique has been proposed as disclosed, for example, in Japanese Patent Application Kokai Publication No. Sho 59(1984)-56741, in which U-shaped trenches of an inter-semiconductor-element isolation region and a collector isolation region are simultaneously formed. With reference to FIGS. 1A-1G, the conventional semiconductor device manufacturing method will now be described.
FIGS. 1A-1D are cross-sectional views arranged in sequential order of steps A-D of a process for manufacturing a conventional semiconductor device, that is, cross-sectional views arranged in sequential order of steps of the process for obtaining a dielectric isolation structure of the prior art. FIGS. 1E-1G are cross-sectional views arranged in sequential order of steps E-G following the previous steps, that is, cross-sectional views arranged in sequential order of steps E-G of the process for manufacturing a bipolar transistor.
In the conventional semiconductor device manufacturing method, as shown in FIG. 1A, an n-type buried layer 2 having a film thickness of 1.5 .mu.m is first formed on a principal surface of a p-type silicon substrate 1. An n-type epitaxial layer 3 having a thickness of 1.5 .mu.m is then deposited on that n-type buried layer 2. Subsequently, three layers, namely, a silicon dioxide film 45 having a thickness of 0.15 .mu.m, a silicon nitride film 46 having a thickness of 0.35 .mu.m and a PSG (phosphosilicate glass) film 47 having a thickness of 1 .mu.m are stacked in that order on the n-type epitaxial layer 3.
As shown in FIG. 1B, this assembly is then subjected to Reactive Ion Etching (hereinafter referred to as RIE) using a photoresist (not shown in the drawings) as a mask to remove the PSG film 47, the silicon nitride film 46 and the silicon dioxide film 45 located in an element isolation region 48. The assembly is also subjected to RIE using another photoresist (not shown) as a mask to remove only the PSG film 47 located in a collector isolation region 49.
As shown in FIG. 1C, the assembly is subjected to RIE using carbon tetrachloride and boron trichloride, so that a first trench 4, whose bottom surface reaches the inside of the p-type silicon substrate 1, is formed at the element isolation region 48.
At this time, the silicon nitride film 46 and the silicon dioxide film 45 remaining in the collector isolation region 49 cause the etching of that isolation region to be delayed, and hence a second trench 12, which is shallower than the first trench 4, is formed on the n-type buried layer 2 (see step C shown in FIG. 1C).
The thickness of the silicon nitride film 46 and that of the silicon dioxide film 45 are adjusted to such an extent that the bottom of the second trench 12 reaches an upper surface of the n-type buried layer 2.
The n-type epitaxial layer 3 is separated into two regions 3a and 3b through the foregoing steps A-C. Thereafter, the PSG film 47 is removed, and the resulting cross-section of the assembly in this state is as shown in FIG. 1C.
As shown in FIG. 1D, the assembly is subjected to a thermal oxidation treatment, and a silicon dioxide film 50 is formed along the inner surfaces of the first and second trenches 4 and 12. Subsequently, polysilicon 51 is deposited to fill the inside of the first and second trenches 4 and 12, and the assembly is then etched back to eliminate the polysilicon other than that portion existing inside the first and second trenches 4 and 12.
The assembly undergoes a thermal oxidation treatment, so that a silicon dioxide film 56 is formed on the surface of the polysilicon 51. The silicon nitride film 46 is then removed. The resulting cross section of the assembly at this time is shown in FIG. 1D.
An isolation structure of the prior art is thus obtained through the foregoing steps A-D.
One example of a conventional method when a bipolar transistor is manufactured by the use of this dielectric isolation structure is shown in FIGS. 1E-1G.
Following the process D shown in FIG. 1D, a high density of n-type impurities are implanted into the region 3b of the n-type epitaxial layer 3 by ion implantation, so that an n.sup.+ -type collector region 16 is formed as shown in FIG. 1E. A silicon dioxide film 7 is deposited, and the silicon dioxide films 7 and 45 are etched using a photoresist (not shown) as a mask, whereby an opening 9 is formed over the n-type epitaxial layer 3a.
After that, p.sup.+ polysilicon containing boron (B) is deposited on the opening 9, and the P.sup.+ polysilicon film thus deposited is patterned using a not-illustrated photoresist as a mask. Subsequently, a silicon dioxide film 18 is deposited over the entire assembly. The cross section of the assembly in this state is shown in FIG. 1E.
The silicon dioxide film 18 and the p.sup.+ polysilicon film 17 located at the area surrounded by the opening 9 are etched away using a not-illustrated photoresist as a mask, whereby an emitter opening 19 is formed as shown in FIG. 1F.
An intrinsic base region 21 is formed by ion implantation or the like, and an emitter sidewall 22 is formed. Polysilicon containing arsenic (As) is then deposited, and the polysilicon film thus deposited is patterned using a not-illustrated photoresist as a mask, so that an emitter polysilicon 23 is formed.
Subsequently, an emitter region 24 and an external base region 20 are formed by a heat treatment. The cross section of the assembly at this time is shown in FIG. 1F.
As shown in FIG. 1G, after a silicon dioxide film 44 has been deposited, a wiring contact hole 25 is formed using a not-illustrated photoresist as a mask.
Aluminum is then deposited and patterned using a not-illustrated photoresist as a mask, so that an aluminum wiring 27 is formed. The cross-section of the assembly at this time is shown in FIG. 1G.
The bipolar transistor is completed through the above explained steps E-G shown in FIGS. 1E-1G.
FIG. 2 is a plan view showing a conventional bipolar transistor thus obtained. A cross-sectional view taken along a line 1G-1G shown in FIG. 2 corresponds to that shown in FIG. 1G. Reference numerals used in FIG. 2 are identical with those used in the aforesaid steps A-G. In FIG. 2, numeral 4a denotes an outer periphery of the first trench 4 while 4b denotes an inner periphery of the same.
According to the conventional semiconductor device manufacturing method set forth in the above, it should be noted that different photoresist masks are used for the formation of the first trench 4 and the second trench 12 (see FIGS. 1B and 1C), respectively. A further photoresist mask is also used in forming the opening 9 (see FIG. 1E).
Thus, where different photoresist masks are used in this way, it is necessary to align the photoresist masks. However, such a positional alignment usually involves an error of approximately 0.2 .mu.m.
In the foregoing semiconductor device manufacturing method, there are errors of about 0.2 .mu.m between the patterns for the first trench 4 and the second trench 12 and also between the patterns for the first trench 4 and the opening 9. There is a maximum error of 0.4 .mu.m between the second trench 12 and the opening 9.
These errors lead to the undesirable situation where the opening 9 will be formed on either the first trench 4 or the second trench 12, and insulation failure will occur, thereby leading to defectives.
To cope with such an alignment error, that is, defective semiconductor devices caused by insulation failure, it is necessary to assure an allowance for alignment between patterns in a conventional semiconductor device.
In such a conventional semiconductor device, because of the necessity of such an allowance, it is impossible to reduce a space to less than 0.4 .mu.m between the first trench 4 and the opening 9. As a result of this, a junction capacitance between the external base region 20 and the n-type epitaxial layer 3 also occurs along the outer periphery of the external base region 20. Even when the external base region 20 was finely miniaturized, it failed to reduce a parasitic capacitance between a base and a collector.